1. Field of the Invention
This disclosure is concerned with nonvolatile semiconductor memory devices, which in particular relates to a NAND-type nonvolatile semiconductor memory device with improved reliability by reducing a potential difference between the substrate and selection transistors during an erasing operation.
2. Discussion of Related Art
There are increasing demands for nonvolatile semiconductor memory devices that are electrically erasable and programmable and retain their data even without power supplies. Specifically, NAND-type nonvolatile semiconductor memory devices are widely used in portable information and communication apparatuses because they are capable of containing large quantities of data in limited sizes.
FIG. 1 is a cross sectional diagram showing the structure of a cell string ST in a conventional NAND-type semiconductor memory device. Referring to FIG. 1, in the cell string ST formed in a substrate 13 of p-well, a ground selection line (GSL) 31, a wordline WL of memory cells MCs, and a string selection line 33 are arranged in order between a common source line (CSL) 15 and a bitline (BL) 17.
In this structure, the ground selection line (GSL) 31 and the string selection line (SSL) 33, and adjacent structures form parasitic capacitances. In FIG. 1, the reference numerals C1, C2, and C3 denote capacitance values on the ground selection line (GSL) 31, which are formed with the substrate 13, the common source line (CSL) 15, and the wordline WL1, respectively. And, in FIG. 1, the reference numerals C1′, C2′, and C3′ denote capacitance values on the string selection line (SSL) 33, which are formed with the substrate 13, the bitline (BL) 17, and the wordline WL32 respectively. Here, the capacitance values C1, C2 and C3 may be similar to the capacitance values C1′, C2′ and C3′.
FIG. 2 is a diagram showing voltage levels applied while erasing data in the conventional NAND-type nonvolatile semiconductor memory device, and other induced voltage levels. In FIG. 2, the solid lines depict the applied voltage levels while the broken lines depict the induced voltage levels.
Referring to FIGS. 1 and 2, an erasing voltage Vers is applied to the substrate 13 and a ground voltage VSS is applied to a wordline WLi of the cell string ST. A voltage Vers-Vbi≈Vers induced on the common source line (CSL) 15 and the bitline (BL) 17, with a forward-biasing current from the substrate 13 to an n+ region 41. Here, Vbi represents the built-in potential between the substrate 13 and the n+ region 41.
By the conventional method of erasing data, the ground selection line (SSL) 31 and the string selection line (SSL) 33 are conditioned in floating states. Thus, in the data erasing operation, the ground selection line (GSL) 31 and the string selection line (SSL) 33 are set to about βVers. As a result, the voltage difference about (1−β)Vers is established between the ground selection line (GSL) 31 and common source line (CSL) 15, and between the string selection line (SSL) 33 and the bitline (BL) 17. Here, β is (C1+C2)/(C1+C2+C3) or (C1′+C2′)/(C1′+C2′+C3′) for the ground selection line (GSL) 31 or the string selection line (SSL) 33, respectively.
As nonvolatile semiconductor memory devices become highly integrated, spatial distances between the ground selection line (GSL) 31 and wordline WL1 and between the string selection line (SSL) 33 and the wordline WL32, gradually become narrower. As a result, the capacitance values C3 and C3′ become larger and the value of β, approaches 0.5. As a result, the electric fields between the ground selection line (GSL) 31 and common source line (CSL) 15, and between the string selection line (SSL) 33 and the bitline (BL) 17 are increased.
Accordingly, with the conventional method of erasing data in the NAND-type nonvolatile semiconductor memory device, a breakdown effect in insulation films between the ground selection line (GSL) 31 and the common source line (CSL) 15 and between the string selection line (SSL) 33 and the bitline (BL) 17 may occur. Further, the breakdown effect may occur in insulation films between the substrate and the selection lines GSL and SSL. As a result, the conventional method of erasing data is disadvantageous because it may degrade the reliability of erasing operation in the device.